1. Field of the Invention
The present invention is directed to a model of a transistor that can be used to account for gate resistance and/or gate resistance induced propagation delay.
2. Description of the Related Art
Transistors suffer from a switching delay due to the resistance of the gate. This delay is called gate resistance induced propagation delay (GRID). Standard performance modeling or simulating of transistors has typically ignored GRID because other delays have been of such magnitude that GRID was insignificant. However, as device dimensions are scaled down (e.g. sub-half micron CMOS technology) GRID has become a more significant percentage of a transistor's total switching delay.
When simulating a circuit that includes transistors, an RC lumped model is conventionally used to account for distributive RC line delays. However, the RC lumped models is not a practical means for simulating GRID because it does not account for the width effect of the transistor and it unreasonably slows down the simulation.
Therefore, an efficient model of a transistor is needed that can be used to account for gate resistance induced propagation delay.